抗差分功耗分析攻击的AES S盒电路设计

Design of AES S-box Circuit with Anti-DPA Attack

提出一种抗差分功耗分析攻击的高级加密标准(AES)异步S盒电路。采用复合域算法实现精简的S盒结构,通过引入单轨异步流水线降低整个S盒的功耗,在单轨电路中局部采用异步双轨电路,利用随机数控制下的数据扰乱机制,改善电路的抗差分功耗分析攻击性能,建立S盒差分功耗分析攻击仿真平台,对设计的相关性能进行了仿真验证和测试。

This paper proposes an asynchronous Advanced Encryption Standard（AES） S-box circuit with the performance of anti-Differential Power Analysis（DPA） attacks.In this S-box,composite-field arithmetic is used to attain the compact S-box architecture,the single-rail asynchronous pipelines are inserted in the data-path circuits to reduce the S-box circuit’s power,its property of anti-DPA attack is improved by introducing the locally inserting asynchronous dual-rail circuits and the disordered-data mechanism.Simulating validation and test are done by the presented simulating DPA attack platforms for the S-box.