基于Nios Ⅱ处理器的B码解调设计

B Code Demodulation Design Based on Nios Ⅱ Processor

针对国内试验靶场对时统终端硬件结构的复杂性,从工程实施的角度改进原有时统终端码解调设计和控制方案。在严格遵循国军标中时统终端性能指标的前提下,对系统的设计进行硬件结构的简化和控制器的改进。实现时统终端基于FPGA中NiosⅡ嵌入式处理器软核的集成化设计,完成IRIG-B(DC和AC)码解调。

Pointing at the complexity of time unified and terminal system’s hardware architecture of the shooting range,this paper improves the original solution of the design technique of IRIG-B decodulation and system control,in terms of project implementation.Under the premise of observing GJB,it simplifies the hardware structure and innovates in design of system.It realizes the practice of integrated design time unified and terminal system based on FPGA’s Nios Ⅱembedded processor,and finishes decoding IRIG-B code（DC and AC）.