基于SoC规范的存储器内建自测试设计与对比分析

Comparative analysis and design for memory built-in self test based on specification of SoC

集成电路深亚微米工艺技术和设计技术的迅速发展使得SoC存储器的测试问题日益成为制约其技术发展的"瓶颈"。为解决SoC中存储器走线和多IP核测试等问题,本文从嵌入式核测试标准IEEE P1500出发,采用了基于该规范的专用硬件方式内建自测试的设计及实现方法,并通过与传统的存储器内建自测试结构进行比较和分析,证明了基于该规范的内建自测试方案可以在满足功耗约束下减少走线,实现多IP核测试。

With the rapid development of deep submicron meter manufacture technology and design technology of integrated circuits,the test of memories embedded in SoC has been the choke point of technology development on SoC.In order to solve the problems of the memory alignment and the test of Multi-IP core,the paper introduces an embedded core test standard-IEEE P1500.Combined with the standard,the hardware-centric approaches for embedded memory is adopted. Then,the traditional structure of MBIST is compared with the hardware-centric approaches to analyzing the advantage of the hardware-centric approaches.The comparison show that the hardware-centric approaches can reduce the alignment and test the Multi-IP core under the condition of the power constraints.