低功耗宽调谐范围锁相环设计

Design of a Low Power Wide-Range Phase-Locked Loop

针对传统锁相环输出频率范围有限、功耗大的缺陷,通过对压控振荡器震荡机理进行理论分析,设计了一款用于时钟发生器的低功耗、宽调谐范围、低相位噪声锁相环。该锁相环采用了新型可编程、低调谐增益、低功耗的环形振荡器,达到了宽频率输出范围、低相位噪声、低功耗的目的,采用SMIC公司0.18um混合信号工艺,用Cadenced的Hspice仿真工具进行仿真,在1.8V电源电压供电情况下获得了50MHz-1.7GHz的频率锁定范围和1.8mW-2.3mW的较低功耗。单边带相位噪声在10KHz频偏处为-104dBc/Hz.。

Is limited in view of the traditional phase-locked loop output frequency range,the power loss big flaw,through controls the oscillator to the pressure to shake the mechanism to carry on the theoretical analysis,designed one section to use in the clock generator the low power loss,the broad tuning scope,the low phase noise phase-locked loop. This phase-locked loop has used new programmable,the low harmonious gain,the low power loss ring oscillator,has achieved the wide band rate output range,the low phase noise,the low power loss goal,uses SMIC Corporation 0.18um composite signal craft,carries on the simulation with the Cadenced Hspice simulation tool,has obtained the 50MHz~1.7GHz frequency locking range and the 1.8mW~2.3mW low power loss in the 1.8V supply voltage power supply situation. The single side band phase noise in the 10KHz frequency offset place is 104dBc/Hz.