基于FPGA的自适应谱线增强系统设计

Design of Adaptive Line Enhancement System Based on FPGA

在此基于Altera公司的现场可编程门阵列(FPGA)芯片EP2C8F256C6,采用最小均方算法设计了自适应谱线增强(ALE)处理系统。以FPGA为处理核心,实现数据采样控制、数据延时控制、LMS核心算法和输出存储控制等。充分利用FPGA高速的数据处理能力和丰富的片内乘法器,设计了LMS算法的流水线结构,保证整个系统具有高的数据吞吐能力和处理速度。并且通过编写相应的VHDL程序在QuartusⅡ软件上进行仿真,仿真结果表明该设计可以快速、准确地实现自适应谱线增强。

In this article,an adaptive line enhancer（ALE） system using LMS algorithm is designed,based on Altera corporation′s Field Programmable Gate Array（FPGA） EP2C8F256C6.The data sampling control,data delay control,LMS algorithm and output memory control are implemented with FPGA as the processing center.The pipeline structure of LMS algorithm is designed through taking the advantages of the high-speed data processing and the rich volume of embedded multipliers of the FPGA,to make sure the whole system has huge data throughput and fast processing capacity.Besides,the system was simulated with the software Quartus II by writing the corresponding VHDL program.The simulation shows that this design can implement ALE rapidly and accurately.