摘要
当前的VLSI数字信号处理器都以乘加器为运算单元,去完成各种正交变换,常会遇到稳定性问题。该文提出了一类新型的以快速旋转器为运算核的VLSI变换微处理器,它能以最佳的数值稳定性高效地完成用Givens旋转序列实现的各种正交变换。结合图像处理应用的实际需要,设计了包含三个并行的TFE变换机的PTFE试验芯片,采用0.8μm双层金属CMOS工艺制造,测试表明,功能正确,工作频率达到40MHz,具有高达960×106s-1移加的运算吞吐率。芯片具有高度的灵活性、可编程性和可扩展性。与该芯片配合,开发了一个针对图像处理中常用变换、按照PTFE硬件控制信号格式产生指令序列的编译器。
Current VLSI digital signal processors perform various orthogonal tramsforms using multiplier accumularor as the arithmetic unit, which often suffers from robustness problem. A new type VLSI transform microprocessor using the fast rotator as the arithmetic core is presented. It can very efficiently perform various orthogonal transforms by Givens rotation sequence with the best robustness. Based on image processing application a PTEE experimental chip is designed, which includes three parallel transform engines. It is fabricated by using 0.8μm double layer metal CMOS technology. The functionality of the chip tested is correct. The chip can work at the frequency of 40MHz with high throughput of 960million shift addition operations. PTEE chip is flexible, programmable and extendable. Equipped with the chip, a compiler is developed to generate the instruction sequence according to the format of PTFE control signals for the frequently used orthogonal transforms in the image processing.
出处
《清华大学学报(自然科学版)》
EI
CAS
CSCD
北大核心
1999年第1期67-70,共4页
Journal of Tsinghua University(Science and Technology)
基金
国家自然科学基金
关键词
正交变换
快速旋转器
运算核
VLSI
变换微处理器
orthogonal transform
lapped orthogonal transform
fast rotation
fast decomposition algorithm
systolic array