一种新复用型模糊控制器VLSI设计

Applicable VLSI Architecture for Fuzzy Micro Controller

本文提出了一种模糊化器复用的模糊控制器（ＦＭＣ）的ＶＬＳＩ设计．这一ＡＳＩＣ电路利用模糊处理特点，采用模糊化器复用的结构，在系统的实现规模不变的情况下大大提高了系统性能．同时由于采用了并行流水线和控制ＦＡＴ表等技术，可以获得每６个时钟至少８条模糊规则的处理速度．基于硬件描述语言ＶＨＤＬ的模拟和综合结果表明，采用１．５μｍＣＭＯＳ工艺时，电路的规模约为２０ｋ单元面积（内含２ｋＲＡＭ），在最坏情况下，最高时钟频率约可达３０ＭＨｚ，数据处理速度达到４０Ｍ条规则／秒．

Abstract A specific VLSI architecture with reusable fuzzier for fuzzy micro controller is presented. It uses the properties of fuzzy process, and adopts the structure with reusable fuzzier, so it has better performances than the chip of NLX230 produced by Neuralogix Company in the same chip size. In addition, the pipeline has been adopted and uses the architecture of control file access table which results in a high throughput at eight pieces of fuzzy rules every six clocks.This circuit is simulated by the hardware description language(VHDL). then synthesis results show that the IC chip contains about 20k unit area (include 2k RAM), the speed of data processing can reach 40M rules/s when 1.5μm CMOS process technology is used.