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CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION

CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION
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摘要 The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively. The pattern run-length coding test data compression approach is extended by introducing don't care bit (x) propagation strategy into it. More than one core test sets for testing core-based System-on-Chip (SoC) are unified into a single one, which is compressed by the extended coding technique. A reconfigurable scan test application mechanism is presented, in which test data for mul- tiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added. The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks, and to an ITC' 02 benchmark circuit. Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve test data compression/decompression, but also reduce the redundant shift and capture cycles during scan testing, decreasing SoC test application time effectively.
出处 《Journal of Electronics(China)》 2010年第1期79-87,共9页 电子科学学刊(英文版)
基金 Supported by the National Natural Science Fund of China (No.60876028) the key Project of Natural Science Foundation of the Anhui Higher Education Institutions (No.KJ2010A280)
关键词 System-on-Chip(SoC) Test application time Pattern run-length X-propagation Union test RECONFIGURATION System-on-Chip (SoC) Test application time Pattern run-length X-propagation Union test Reconfiguration
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参考文献12

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