一种设计同步时序电路的新方法

A New Method for Designing Synchronous Sequential Circuits

介绍了一种设计同步时序逻辑电路的新方法。该方法之关键在于直接从时序电路的状态转换图（ＳＴＤ）获得Ｊ－Ｋ、Ｄ和Ｔ触发器的激励方程式。采用该方法设计了几个实例，并由此验证了其正确性和有效性。

A new method for designing synchronous sequential circuits(SSC′s)is described.The crux of this method is that excitation equations for J K,D and T flip flops are obtained directly from the state transition diagrams(STDs).The correctness and effectiveness are testified by several SSC′s designed using the new method.