单载波超宽带下判决反馈均衡器芯片优化设计

ASIC design optimization of a decision feedback equalizer at single-carrier ultra-wide band

单载波超宽带通信系统的均衡在芯片实现中面临高吞吐率、高性能和低复杂度3方面问题。该文从广播结构电路表达、delayed-sign-LMS系数更新算法和寄存器重采样芯片设计方法学3个角度提出一种适合芯片实现的判决反馈均衡(DFE)结构。该结构以标准LMS-DFE为基础,克服自适应反馈滤波器中迭代界对吞吐率的影响,解决广播结构中输入高扇出带来的延时和功耗问题。仿真结果表明:与直接结构LMS-DFE相比,该结构性能损失在0.1dB之内。芯片综合表明,基于Smic.18 CMOS工艺,吞吐率达到125Mb/s,与广播结构delayed-LMS-DFE相比,面积减少23%,功耗降低33%。

Chip design of single-carrier ultra-wide band equalization has to resolve problems resulting from the high throughput rate,high performance and low complexity. A structure suitable for ASIC implementation for a decision feedback equalizer （DFE） was developed based on the transposed structure of circuit presentation,the delayed-sign-LMS algorithm and the register resample of ASIC design methodology. The structure,using the standard LMS-DFE,eliminates the effect of the iteration bound on the throughput rate,which exists in adaptive filters containing feedback loops,and solves the problem of delay and power consumption due to high input fan out in transposed items. Simulations show that the BER performance loss is less than 0.1 dB compared with the standard-LMS. The synthesized result in a 0.18 μm CMOS process shows that the area and power consumption items are improved by 23% and 33% compared with the transposed delayed-LMS item,with the speed reaching 125 Mb/s.