可配置语音识别输出概率计算协处理器的设计

Design of a configurable output probability calculation coprocessor for speech recognition

在基于连续隐含Markov模型的嵌入式语音识别系统中,为提升计算效率、降低系统功耗,将算法中计算消耗最大的输出概率计算模块作为协处理器实现。通过先入先出队列电路隔离输出概率计算中的Markov距离和对数加法的数据通路使得系统参数可以灵活配置,并根据输出概率计算所需参数的地址产生规则设计了地址产生单元。采用Xilinx Virtex-5系列FPGA实现了该输出概率协处理器,并通过S3C44B0X微控制器验证了该设计。在配置参数为3维Gauss混合分量、27维特征矢量的条件下,对358个状态,协处理器工作在27MHz的时钟频率时计算输出概率的处理速度达到了0.13倍实时。

The most time-consuming output probability in embedded speech recognition systems based on the continuous hidden Markov model was computed using a configurable co-processor to promote the computation efficiency and lower the system power consumption. The output probability calculation （OPC） includes the Mahalanobis distance and the add-log modules with a FIFO used to separate these two circuits,therefore,making the designed system more configurable. The address generation unit was also specially designed for the OPC. The coprocessor was implemented on the Xilinx Virtex-5 and verified by using S3C44B0X as a host controller. Experiments show that the coprocessor costs 0.13 real-time to calculate 358 states＇ output probabilities with 3-D Gaussian mixtures and 27-D speech feature vectors and with clock of 27 MHz.