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考虑电压降的SoC布局规划算法

SoC Floorplanning with IR-drop Consideration
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摘要 针对SoC布局中的电压降问题,根据SoC布局特点以及芯片电压降物理模型,提出一种模块选择策略和目标函数共同约束算法.该算法在实现SoC布局的同时,极大降低了芯片的电压降,有效提高后端设计的收敛速度.实验结果表明了该算法的有效性. The SoC floorplan with IR-drop consideration is studied. Based on the configuration of SoC circuit and the physical compact 1R-drop model, a constraint algorithm developed. The proposed algorithm greatly reduces the IR-drop of circuit and then improves the convergence of physical design. Experimental result shows the effective- ness of the proposed algorithm.
作者 陈珊珊 周晓方 荆明娥 王琳凯
机构地区 复旦大学专用集成电路国家重点实验室
出处 《复旦学报（自然科学版）》 CAS CSCD 北大核心 2010年第2期236-241,共6页 Journal of Fudan University：Natural Science
基金 国家自然科学基金(60876016 60773125) 专用集成电路与系统国家重点实验室(ZD20080103 GF20080306) 宁波市自然基金(2009A610059)资助项目
关键词 布局规划 系统级芯片 B—tree 电压降 floorplan SoC B-tree IR-drop
分类号 TN401 [电子电信—微电子学与固体电子学]
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参考文献8

  • 1Wong D F, Liu C L. A new algorithm for floorplan design [C] // Proceedings of ACM/IEEE Design Automation Conference (DAC). Las Vegas, NV, USA: IEEE Computer Society Press, 1986: 101-107.
  • 2Chang Y C, Chang Y W, Wu G M, et al. B^* -tree:A new representation for non-slicing floorplans [C] // Proceedings of ACM/IEEE Design Automation Conference (DAC). Los Angeles, CA, USA: ACM press, 2000: 458-463.
  • 3曾宏,曾璇,闵昊.超深亚微米下百万门级系统级芯片的物理设计方案[J].复旦学报（自然科学版）,2006,45(1):26-29. 被引量：2
  • 4Lin J M, Yi H E, Chang Y W: Module placement with boundary constraints using B^* -trees [J]. IEEE Proceedings Circuits, Devices & Systems, 2002,149(4) : 251-256.
  • 5Dong C S, Kyung L H, Gi J J. Efficient modeling techniques for IR drop analysis in ASIC design [C]// Proceedings of IEEE International ASIC/SOC Conference. Washington, DC, USA: IEEE press, 1999: 64- 68.
  • 6Bhooshan R. Novel and efficient IR-drop models for designing power distribution network for sub-100 nm integrated circuits [C] // Proceedings of 8th International Symposium on Quality Electronic Design (ISQED'07). San Jose, CA, USA: IEEE Computer Society press, 2007: 287-292.
  • 7Shakeri K, Meindl J D. Compact physical IR-drop models for chip/package co-design of gigaseale integration (GSI) [J], Electron Devices, 2005,52(6) : 1087-1096.
  • 8Chen J, Zhao C H, Zhou D, et al. Floorplan with IR-drop consideration [C] // Proceedings of WSEAS/ IASME Int. Conference on System Science and Simulation in Engineering (ICOSSSE 2005). Tenerife, Canary Islands, Spain: WSEAS Press, 2005: 150-155.

二级参考文献4

  • 1Sapatnekar S S,Su H H.Analysis and optimization of power grids[J].IEEE Design and Test of Computers,2003,20(3):7-15.
  • 2Xiong J J,He L.Full-chip routing optimization with RLC crosstalk budgeting[J ].IEEE Trans on CAD of integrated circuits and systems,2004,23(3):366.
  • 3Preston W K,Trybula W J,Athay R N.Design for semiconductor manufacturing-perspective[J].IEEE Trans on components,packaging,and manufacturing technology,1997,20(1):58-60.
  • 4Rabaey J M,Chandrakasan A,Nikolic B.Digital integrated circuits-a design perspective[M].Beijing:Pearson education aisa limited and tsinghua university press,2004.

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复旦学报（自然科学版）
2010年 第2期

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