一种CMMB系统信道估计与均衡器实现方案

An Algorithm and Its VLSI Implementation of Channel Estimation and Equalization for CMMB System

提出了一种针对CMMB系统的信道估计和均衡方案,信道估计在时域上采用2种插值算法根据条件可选的方法,以提高其性能.给出了仿真结果,并给出了相应的硬件实现结构和综合结果.根据FPGA验证结果,这一针对CMMB的信道估计和均衡方案可以抗多普勒频移400 Hz以上.在200 Hz多普勒频移,15 dB信噪比的条件下,其误比特率可以达到0.4%(BPSK调制,TU-6信道)和1%(QPSK调制,TU-6信道).整个模块规模约为64.5万门.其中memory部分复用了系统已有的memory 98304比特(约12.5万门).

An algorithm of channel estimation and equalization for CMMB system is proposed, in which two interpolation methods are employed in the time domain based on the condition choosable method to improve its performance The simulation results and hardware architecture, as well as synthesis results of VLSI implementation are given here The FPGA verification results show that it can overcome more than 400 Hz of Doppler frequency shift. In the case of 200 Hz of Doppler frequency shift and 15 dB SNR, the BER for TU-6 channel is 0. 4% （BPSK modulation） and 1% （QPSK modulation） respectively. The whole chip area is about 3.87 mm2 （in SMIC 0. 13μm library）.