数字图像中值滤波算法的FPGA实现

Implementation of Median Filter on FPGA

针对传统中值滤波算法排序量大的缺点,详细研究了一种改进的中值滤波算法,对一个n×n的滤波窗口,先对每一列升排序,再对每一行升排序,最后取对角线上像素中值作为滤波结果。用Verilog硬件描述语言实现改进的中值滤波算法,并在Modelsim6.5a中通过时序仿真,最终在Altera DE2开发板上验证和实现。

In order to solve the problem that the speed of classical median filter was slow because of lots of sorting,an improved median filter algorithm is described.For a filter window,each row is sorted up first,and then each line,the median value in the cater corner is the result.Verilog HDL code of the improved median filter algorithm is implemented and simulated in the Modelsim 6.5a IDE,validated and realized on the Altera DE2 board.