大规模集成电路中开闭路测试的优化与改进

Optimization and Improvement in Open/short Test in High Volume Manufacture

现有的直流开闭路测试无论在测试时间还是测试效率上已经遇到了很大的瓶颈,其测试时间将近1s,导致整体的测试时间很长,极大地影响了产能。文章介绍的动态开闭路测试以及VTT终端开闭路测试在测试流程以及测试方法上做了很大的优化和改进,从而很好地解决了测试时间上的瓶颈问题。通过对相同被测芯片测试数据的比较后发现,这一改进对大规模生产的半导体工厂来说是一个显著降本增效的方法,对于一个批次的芯片,节约的时间可以达到40min。除此之外,这种动态测试方法还可以普及到其他静态直流测试项中,由此在测试时以及测试效率上所得到的优化是显而易见的。

Current DC open short test meets the bottleneck in both test time and test efficiency and its test time is nearly 1 second which causes long test time of the whole flow leading to negative impact on the manufacture delivery. In this paper, we will introduce the dynamic open short test and Vττ Terminal open short test which are improved on both test methodology and test flow, and it will solve the bottleneck we mentioned above. Based on the test data comparison on the same unit, we find that these test methodology will obviously improve the efficiency and lower the cost to the semiconductor high volume manufacture. The reduction time will arrive 40 minutes if we run the whole lot. Besides that, this dynamic methodology can also be used on other static DC test items and it will lead to more improvement on the test time and test efficiency.