改进Tent混沌序列的数字电路BIST技术

BIST technique of digital circuits based on improved tent chaotic sequence

针对目前数字电路规模变大,测试困难的特点,提出了一种基于改进Tent混沌序列的数字电路BIST技术.采用改进混沌Tent映射模型构建硬件电路并产生具有白噪声特性的"0-1"随机序列作为数字电路的自动测试生成图形,利用CRC特征电路分析输出响应,并得到混沌序列的测试响应特征码,通过特征码的不同来检测故障.研究表明,本文方法易于BIST技术实现,相比于普通M序列性能优越,能够得到更高的故障检测率和故障隔离率,适合于FPGA等大规模可编程逻辑电路的自动测试.

This paper proposed a realization method of BIST technique of digital circuits based on improved Tent chaotic sequence to address the problem of testing digital circuits.Random sequence of＂0 -1＂with white noise characteristics which generated by improved tent chaotic logistic map model hardware implementation is used as automatic test pattern generation （ATPG） of digital circuits.Test response signatures of chaotic sequence are obtained from CRC analysis of output response.It is shown that the method presented in this paper is easy for realization of BIST and has superior performance of higher rate of fault detection and fault isolation than that of M sequence.It is suitable for large-scale FPGA and automatic testing of other programmable logic circuits.