基于VHDL卷积交织器的设计与实现

VHDL Design and Implementation of Interleaver

研究交织的原理,提出了一种VHDL来实现DOCSIS标准中的卷积交织器的方案,并且在ModelSim SE6.1d环境下进行功能仿真,该方法具有实现简单和占用资源少等优点.

This paper introduces the principle of interleaver and the VHDL inplement of interleaver in DOCSIS systems,and the effect of the implementation is proved through function simulation by using Model Sim SE 6.1d.The design has advantages of easy realization and less resource consumption.