一种高效、可重构的二—十进制转码器设计

An Efficient and Reconfigurable Design of Binary to Decimal Converter

文中针对二—十进制(BCD)转码器的FPGA实现目标,提出了一种高效、易于重构的转码器设计方法.并在FPGA(Altera EP1K30QC208-2)开发板上成功地实现了该设计,验证结果表明;和其它4种方法实现的12-bit二—十进制转码器相比,这种设计不但能节约实现代价(逻辑单元LEs);而且也能减小电路的路径延迟。

In order to implement binary, to decimal （Binary Coded Decimal, BCD） converter on a Field Programmable Gate Array （FPGA） chip, an efficient and easily reconfigurable design is proposed. Moreover, the 12-bit binary to decimal converter was successfully implemented on a FPGA development board （Ahera EP1K30QC208-2）. Experimental results show that compared with other four designs, the design can save of the Logic Elements （LEs）. Meanwhile, Time Propagation Delay （TPD） can decrease.