一种适于FPGA实现的中值滤波及软硬件协同仿真

A Median Filtering Suiting for FPGA Implementation and Its Hardware and Software Co-simulation

针对中值滤波处理图像时存在的缺陷,提出了一种基于简单椒盐噪声滤波算法的极值中值滤波算法,通过对256×256×8 bits的Lena图像和Link for ModelSim仿真验证了该算法的处理效果.结果表明,该算法能很好地滤除椒盐噪声和保护图像细节,易在FPGA上实现,提高了图像的处理速度.另外,为了加快系统的功能验证,在系统仿真中使用Link for ModelSim组件,打破了软硬件间的屏蔽,节省了仿真时间.

For the problems that exist in processing images using median filtering method,a new median filtering algorithm based on document [5] extreme value was presented,and using Lena image with 256×256×8 bits and the simulation software Link for ModelSim,the validity of this algorithm was tested.The results show that,the algorithm has goodly filtered salt and pepper noise,and can protect images detail,and can easily realized in the FPGA,and the image processing speed is raised.Then,in order to accelerate the simulation verification speed,Link for ModelSim components were used in this system,which broke the barrier between hardware and software,and saved simulation time.