超薄芯片叠层封装器件热可靠性分析

Analysis of thermal reliability for ultrathin chip stacking package device

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。

The distribution of thermal stress and warpage in one typical kind of ultrathin chip stacking package device,which was subjected to reflow soldering,was simulated and analyzed using a common finite element software MSC.Marc.The effects of thickness variation of some components on the thermal stress and warpage of stacked ultra-thin chip within the device were studied.The results show that,in the package device,the maximum thermal stress（116.2 MPa） appears at the bottom passive chip,while the largest warpage（0.028 26 mm） appears in the upper corner of EMC（epoxy molding compound）.Appropriately increasing the thickness of EMC or bottom passive chip or decreasing the thickness of interlayer adhesive reduces the warpage of stacked ultra-thin chip.When the thickness of bottom passive chip is increased appropriately（say 0.01 mm）,its thermal stress is reduced markedly by 10 MPa or more.