改进的CORDIC模块实现的直接数字频率合成器

Direct digital frequency synthesizer based on improved CORDIC module

在传统的定点数流水线型CORDIC算法基础上,就减少迭代次数上提出一种改进算法,实现并行处理时的符号预测。改进算法大大减少了流水线迭代次数,节省了FPGA的Slice Flip Flops数量。最后利用改进算法在Xilinx公司的Virtex-II平台上实现了直接数字频率合成器(DDS)。

An improved algorithm based on the traditional fixed-point pipelined CORDIC-based algorithm is proposed to reduce number of iterations and realize the sign prediction in parallel processing.Improved algorithm not only greatly reduces the pipeline iterations but also saves the number of Slice Flip Flops of FPGA.Finally using this algorithm the Direct Digital frequency Synthesize（rDDS） at Xilinx＇s Virtex-II platform is realized.