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基于FPGA的感应同步器的数据采集和处理的研究 被引量:6

Data Acquisition and Processing for Inductosyn Based on FPGA
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摘要 为了提高感应同步器信号处理系统的可靠性和节省FPGA资源,采用单芯片SOC系统设计,把正/余弦信号电源、A/D控制电路、数据处理集成在一块FPGA内,并通过点对称和轴对称技术优化正/余弦信号电路。研究了一种新型的采样电路和信号处理方法,在激磁信号0°相位时开始采集感应信号,利用FFT计算出感应信号的初相位,即可检测感应同步器的位置。实验证明,设计的电路和信号处理方法正确,只需0~90°的正弦表,分别生成了0~360°的正弦信号和余弦信号,节省了FPGA的资源,只需采集一路感应信号即可实现同步采集激励信号和感应信号的效果。 To improve the reliability of inductosyn signal processing system and reduce FPGA resources,a novel design scheme was proposed.The sine/cosine signal generating circuit for electrical source,A/D control circuit and data processing circuit were integrated into a FPGA,which was based on single-chip SOC technology.And the method of the point symmetry and axial symmetry was used to optimize the sine/cosine signal generating circuit.Then a new sampling circuit and signal processing method were stadied.Induced signal is sampled when the phase of the exciting signal is 0°,and the initial phase of induced signal can be calculated with FFT and then the position of Inductosyn can be obtained.Experiment results conform that the designed circuits and signal processing methods are correct,0° to 360° sine signal and cosine signal are generated that only need the sine table of 0° to 90°,and synchronous sampling the exciting signal and induced signal are achieved that only need to get the induced signal.
机构地区 重庆理工大学
出处 《仪表技术与传感器》 CSCD 北大核心 2010年第5期41-43,50,共4页 Instrument Technique and Sensor
基金 国家自然科学基金项目(50975304) 重庆市自然科学基金项目(2008BB2336) 重庆市教委项目(KJ090609)
关键词 感应同步器 数据采集 FPGA 傅里叶变换 NIOS inductosyn data acquisition FPGA fourier transformation NIOS
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