摘要
介绍了一种新型高速静态存储器——DDRⅡ SRAM(Double Data Rate)的存储器结构、端口设计,并在硬件平台上实现了存储器单时钟读写模式下不同读写时钟的控制实现。该方案实现了工程设计中动态数据的实时更新,并在超宽带雷达信号生成过程中对雷达特征数据的高速读取和实时更新验证了其可行性。
This paper presents the architecture and port design of a static high speed memory：DDRⅡ SRAM （Double Data Rate）,then the control of different single clock read write mode is carried out on the hardware platform. Dynamic real-time data updating in engineering design is achieved in this program,and the feasibility of this program is validated in the real-time high speed data reading mode in ultra-wideband radar signal generating experimentation.
出处
《信息化研究》
2010年第5期17-19,共3页
INFORMATIZATION RESEARCH
关键词
DDRⅡSRAM
读写控制
数据更新
DDRⅡ SRAM
control of read and write operation
data updating
