摘要
分析了时间随机化技术的不足以及掩码技术(功耗随机化)的缺点,在完全防御差分能量攻击的基础上进行基于抗差分能量攻击的设计,提出一种时间和功耗双随机化的电路结构,将其应用在AES算法中,并在FPGA密码芯片、示波器和PC机组成的功耗采集分析平台中进行了验证.结果表明,该电路具备较强的抗差分能量攻击能力.
The problem which time randomization can' t defend differential power analysis completely and the defect of the MASK technique which is usually implemented for the power randomization is analyzed. Based on the absolutely resist differential power analysis, the design should focus on the resource and commonness, the paper propose a time and power randomization circuit, AES algorithm containing this circuit is implemented and is testified in the power collection and analysis system. The result of differential power analysis prove the design to be practical to resist DPA.
出处
《北京工业大学学报》
EI
CAS
CSCD
北大核心
2010年第5期659-663,共5页
Journal of Beijing University of Technology
基金
国家'八六三'计划基金项目资助(2008AA01Z0103)
关键词
差分能量攻击
时间随机化
功耗随机化
AES算法
differential power analysis
time randomization
power randomization
AES cryptography