功耗及信噪比双重约束下ΣΔ模数调制器积分器优化

Parameters Optimization of Integrators in ΣΔ Modulator with Dual Restrictions of SNR and Power Dissipation

针对前馈级联ΣΔ模数调制器结构,详细分析了调制器信噪比及功耗与Class-A类运算放大器构成的各级积分器等效输入噪声功率及功耗间相互关系,并在此基础上提出对于给定调制器信噪比及功耗双重约束的前馈级联ΣΔ模数调制器各级积分器参数参考值的优化选取,包括:采样电容、开关导通电阻、输入晶体管宽长比等,从而有利于低功耗高精度ΣΔ模数调制器设计者确定满足给定功耗和信噪比双重约束的ΣΔ模数调制器优化设计方案,指导晶体管级电路设计,缩短设计周期.

Relations between signal-to-noise ratio and power dissipation of feed-forward cascade ΣΔ modulators and those of switched-capacitor integrators composed of Class-A operation trans-conductance amplifiers are analyzed in detail.Based on the analysis,optimal values of integrators in ΣΔ modulators with both restrictions of signal-to-noise ratio and power dissipation are given in expressions,including：sample capacitor、resistor of switch、ratios of width and length of input transistors and so on.This optimal selection is good for low-power high-resolution ΣΔ ADC designers to have an excellent design with both restrictions,which is also good to give reference to detailed circuit design and reduce design cycle.