一种高速数据接收同步电路的设计

Design of High-Speed Synchronous Circuit for Data Receiving

介绍了一种高速数据接收同步技术,用以解决在高速、超高速情况下数据同步困难的问题。随着电路工作频率的提升,数据的稳定有效周期变得越来越短,对采样时钟的时序要求也越来越高,特别是由于工艺波动、温度变化等原因,数据与时钟的相位关系发生变化,导致时钟采样时发生误码,电路不能正常工作。采用该数据接收同步技术,可以将时钟采样设置为最佳时序,并且当时钟与数据相位关系变化时,能自动对时钟相位进行调节,重新回到最佳时序,从而大大提高数据接收的可靠性。

A high-speed data receiving synchronous technique to overcome difficulties in data synchronization in high-speed and very-high speed applications was described.As operating frequency of the circuit increases,the stable and effective period of data becomes shorter.Therefore,more precise timing is required for sampling clock of the circuit.Especially,due to process fluctuation and temperature variation,phase relation between data and clock may change,which would cause error code in clock sampling and circuit malfunction.Using the data receiving synchronous technique,an optimal time sequence could be obtained.When phase relation between data and clock chenges,clock phase could be automatically adjusted and return to optimal time sequence,which greatly improves the reliability of data receiving.