基于ALU架构的面积优化FIR滤波器设计

Design of Area-Efficient FIR Filter Based on ALU Architecture

提出了一种新颖的基于ALU架构的FIR数字滤波器,这种架构采用存储器和计数器实现FIR滤波器的卷积运算。当FIR滤波器的阶数增加时,该架构的逻辑单元基本不变,存储空间仅线性增加,而不像传统分布式架构的存储空间呈指数增加。因此,这种基于ALU架构的FIR数字滤波器的等效逻辑门数大幅减少。FPGA综合结果表明,当FIR滤波器的阶数大于64阶时,基于ALU架构的FIR滤波器比传统分布式架构的滤波器使用更少的等效逻辑门数。

A novel ALU architecture-based FIR filter was designed,in which convolution operation was realized with memory and counters.With increasing order of FIR filter,logic gate counts remain unchanged,and memory capacity increases linearly,rather than exponentially as in conventional distributed arithmetic（DA） architecture.Consequently,equivalent logic gate counts decreased dramatically in ALU-based FIR filter.FPGA synthesis results show that,when the order of filter is greater than 64 taps,the proposed circuit has far less equivalent logic gate counts than the conventional DA approach.