改进的CMOS工艺功率放大器设计

Design of Improving Power Amplifier for CMOS

本文提出了一种改进的二阶功率放大器的设计,改进的措施主要包括设计无源螺旋形电感、合理运用Cascode电感接入、改进偏置电路的设计。仿真结果为:在P1 dB点,Pout为18 dBm,输入输出匹配的情况下,5.2 GHz的功率增益为30 dB,1 dB压缩点的PAE为16%,输出三阶交调点IP3是26.8 dBm,静态工作电流为252 mA。上述结果表明,改进的功率放大器各项性能指标达到设计的要求。采用TSMC 0.18μm CMOS工艺元件库,应用Cadence软件画出功率放大器电路的版图。上述工作对射频电路的设计有一定的参考价值。

Aim to low efficiency,low integration and more stages of the third-order Power Amplifier,a second-order Power Amplifier is bring forward to ameliorate these shortcomings,The measurements includes the design of passive spiral inductor,rational use of Cascode induetors,improving the bias circuit design.The simulation results are：the output power Pout is 18 dBm in P1 dB point.in the condition of input and output match,the power gain is 30 dB a15.2 GHz,the PAE at 1dB compression point is 16%,the output of IP3 is 26.8 dBm,the total static work current is about 252 mA.These results indicate that the performance of improved Power Amplifier meets the design requirements.These results indicate that improving the performance of the power amplifier to meet the design requirements.Using TSMC 0.18μm CMOS technology library.Cadence goftware applications to draw the map of the two circuits.The work of the RF circuit design have a certain value.