摘要
Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.
Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.
