一个用于高速高精度流水线模数转换器的采样保持电路设计

A sample/hold circuit for high speed and high accuracy pipelined A/D converters

设计了一个可用于高速高精度流水线模数转换器的采样保持电路.运放采用全差分套筒式增益自举,增益可达130 dB,带宽783 MHz.采用栅压自举开关,来减少与输入信号相关的非线性失真,提高线性度.在TSMC0.35μm CMOS工艺下设计,仿真结果表明,在时域内对1 V的阶跃输入电路可以在7 ns内达到误差小于0.012%;在频域内做FFT分析该电路可以达到11.6 bit.

A sample and hold（S/H） circuit for 12 bit 40MS/s pipelined A/D converters was presented. A gain boosted telescopic cascode amplifier was designed. The amplification coefficient is 130 dB and the bandwidth is 782 MHz. A modified boot strapped switch reducing nonlinearity related to input signal was designed. The circuit was simulated and analyzed based on TSMC 0.35 μm CMOS process. The simulation results show that the error of the S/H is less than 0. 012% after 7ns for 1 v step input. The ENOB of the S/H is 11.6 bit in FFT analysis.