摘要
主要针对欧标应答器上传链路的FSK信号,提出了使用FPGA芯片,采用VHDL语言,来实现对FSK信号解调的具体方案。
The article mainly aims at the FSK signal of the European balise up-link, proposes to use the FPGA chip, so that to realize the concrete plan for the FSK signal demodulation with the VHDL language.
出处
《铁路通信信号工程技术》
2010年第3期21-23,共3页
Railway Signalling & Communication Engineering
关键词
应答器
频移键控
数字解调
FPGA
Balise
Frequency-shift keying
Digital demodulation
and Field programmable gate array
