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高速列并行10位模数转换电路的设计 被引量：4

Design of High Speed Column-Parallel 10-Bit ADC
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摘要 设计了用于CMOS图像传感器列级信号处理系统的10位模数转换器.该模数转换电路采用两级转换的方式,转换速度较单斜ADC提高了近8倍.设计了电阻阵列式多路斜坡发生器、级联结构比较器、数字纠错和消失调等电路,该ADC在不增加工艺成本的条件下满足了10位精度的要求.电路采用Chartered 0.35μm工艺制造.测试结果表明,该模数转换器的INL<±0.5 LSB,DNL<±0.5 LSB,信噪比为58.364 7 dB. A novel column-parallel 10-bit ADC used in signal processing system of CMOS image sensor has been proposed in this paper, which has achieved the conversion speed almost 8 times higher than the single-slope ADC by adopting two-stage conversion structure. With the design of circuits including resistor-array ramp generator, cascade comparator, digital correction and offset cancellation, the ADC meets the requirement of 10-bit resolution without increase of processing cost. The proposed ADC was fabricated with Chartered 0.35 ktm technology and test results indicate that its INL〈± 0.5 LSB, DNL〈 ± 0.5 LSB and SNR is 58.364 7 dB.
作者 高静 姚素英 徐江涛 史再峰
机构地区 天津大学电子信息工程学院
出处 《天津大学学报》 EI CAS CSCD 北大核心 2010年第6期489-494,共6页 Journal of Tianjin University(Science and Technology)
基金 国家自然科学青年基金资助项目(60806010) 天津市科技支撑计划重点资助项目(09ZCGYGX01100)
关键词 模数转换器 电阻阵列 失调 比较器 analog todigitalconverter（ADC） resistor-array offset comparator
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

  • 1张娜,姚素英,徐江涛.用于CMOS图像传感器的列并行高精度ADC[J].固体电子学研究与进展,2006,26(3):349-353. 被引量：4
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二级参考文献4

  • 1Mendis Sunetra K.CMOS active pixel image sensors for highly integrated imaging system[J].IEEE Journal of Solid-state Circuits,1997,32(2):187-197.
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  • 4Akira Yukawa.A CMOS 8-bit high-speed A/D converter[J].IEEE Journal of Solid-state Circuits,1985,SC-20(3):775-779.

共引文献3

同被引文献26

  • 1张倩,郭仲杰,余宁梅,吴龙胜.CMOS图像传感器列并行单斜式ADC回踢噪声自补偿方法[J].武汉大学学报（理学版）,2022,68(5):574-580. 被引量：1
  • 2赵文伯,刘俊刚.CMOS图像传感器发展现状[J].半导体光电,1999,20(1):11-14. 被引量：22
  • 3Lim Seunghyun, Lee Jeonghwan, Kim Dongsoo, et al. A high-speed CMOS image sensor with column- parallel two-step single-slope ADCs[J]. IEEE Transac tions on Electron Device, 2009, 56 (3) : 393-398.
  • 4Mendis S K. CMOS active pixel image sensors for highly integrated imaging system[J]. IEEE Journal of Solid- State Circuits, 1997, 32(2): 187-197.
  • 5Snoeij M F, Theuwissen A J P, Makinwa K A A, et al. Multiple-ramp column -parallel ADC architectures for CMOS image sensors [J]. IEEE Journal of Solid-State Circuits, 2007, 42(12): 2968-2976.
  • 6Lee Jeonghwan, Han Gunhee. A/D converter using it- erative divide-by-two reference for CMOS image sen- sor[C] //International SoC Design Conference. USA, 2008 : 35-36.
  • 7Shin M S, Kwon O K. 14-bit two-step successive ap- proximation ADC with calibration circuit for high- resolution CMOS imagers[J]. Electronics Letters, 2011, 47(14) :790-791.
  • 8Furuta Masanori, Nishikawa Yukinari, Inoue Tom, et al. A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D[J]. IEEE Journal of Solid-State Circuits, 2007, 42(4) : 766-774.
  • 9Mase Mitsuhito, Kawahito Shoji, Sasaki Masaaki, et al. A Wide dynamic range CMOS image sensor with mul- tiple exposure-time signal outputs and 12-bit column- parallel cyclic A/D converters [J]. 1EEE Journal of Solid- State Circuits, 2005, 40(12): 2787-2795.
  • 10Matsuo Shinichiro, Bales Timothy J, Shoda Masahiro, et al. 8.9-megapixel video image sensor with 14-b col- umn-parallel SA-ADC[J]. 1EEE Transactions on Elec- tronDevice, 2009, 56(11): 2380-2389.

引证文献4

二级引证文献4

天津大学学报
2010年 第6期

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