基于混沌序列的时序数字电路BIST技术

BIST Technique of Sequential Circuits Based on Chaotic Sequence

提出一种基于混沌序列的时序数字电路的内建自测试(BIST)技术。采用混沌logistic映射模型迭代运算产生具有白噪声特性的"0-1"随机测试序列,将其作为数字电路内建测试的自动测试图形,并利用循环冗余校验(CRC)特征分析电路分析输出响应,从而得到混沌序列测试图形的响应特征码,通过特征码的不同来检测故障。实验研究表明,由于混沌迭代序列测试图形的施加顺序不唯一,因此对于时序数字电路的故障检测而言,能够比普通M序列测试的故障检测率更高,易于BIST技术实现,并适合于FPGA等大规模可编程逻辑电路的自动测试。

This paper proposes a realization method of （Build In Self Test, BIST） technique of sequential circuits based on chaotic sequence. ＂0-1＂Random sequences with the white noise characteristics which generate by chaotic logistic map model suite as digital circuits test pattern. Test response signature of chaotic sequence are obtained from the output response characteristic analysis of （Cyclic Redundancy Check,CRC） circuits. Studies have shown that the chaotic iterative sequence test pattern is not unique to impose order especially for sequential circuits, so the method presented in this paper fault detection rate is greater than that of M sequence and easy for realization of BIST, and suitable for large-scale FPGA and other programmable logic circuits automatic testing.