引入变量卡诺图(VEM)的使用方法及应用

Usage and Application of Introducing Variable Karnaugh Map(VEM)

在逻辑电路的化简和设计中,经常使用的方法是代数法和卡诺图法,但两者在逻辑变量很多的情况下,运用起来显得非常的繁琐,给出VEM的具体的读出规则、合并方法及特殊使用规则,这种方法不仅使多变量函数化简工作更简化,而且使逻辑设计更简单,同时给出VEM的应用实例.

In simplification and design of logical circuit, the frequently used method is by algebra and Karnaugh map. But the both are complex tO use in the cases of logical variable. In this paper, we present read rules, combining methods and special usage rules for VEM. This approach makes the work of multivariable function more simplified and logic design easier, and at the same time, an application example of VEM is given.