数字语音解码器的低功耗设计策略

Low-power design strategy of digital audio decoder

主要从系统级、算法级、结构级等多个层面综合考虑减少数字语音解码器的功耗。系统级使用双向不交叠时钟技术,在提高耗时长的模块运算频率的同时消除了电路的竞争与冒险;算法级主要使用汇编语言重写和优化原代码,既可以压缩源代码,更能充分挖掘硬件的运算潜力;在结构级,主要利用并行技术,增加协处理器进行并行计算,有效提高运算速度。另外在布局布线时使用全定制集成电路设计技术手工布线,大为减少解码器的芯片面积。

This paper is mainly from the system level, algorithm level, architecture-level and other levels to consider a design to lower the digital voice decoder＇s power. The system-level used a two-way non-overlapping clock technology to improve the long time-consuming module＇s operating frequency meanwhile eliminating competition and adventure. The algorithm-level mainly used assembly language to rewrite and optimize the source code which not only can compress the source code, but also can fully tap the potential of computing hardware. The architectural level used parallel technology to increase the co-processor parallel computing, which effectively improved the operation speed. Otherwise using manual routing of full-custom IC layout design, significantly reduced the area of the decoder chip.