期刊文献+

基于RLC π型等效模型的互连网络精确焦耳热功耗计算 被引量:3

An accurate Joule heat model of RLC interconnect based on π equivalent circuit
原文传递
导出
摘要 基于互连网络的RLCπ型等效模型,考虑电感的屏蔽作用和非理想的阶跃激励,提出了互连线网络在斜阶跃激励下的焦耳热功耗计算方法,极大地简化了互连网络中电流和功耗的表达式.基于90nm金属氧化物半导体(CMOS)工艺的互连参数对所提出的计算方法进行了计算和仿真验证,对于上升信号小于1ns的情况,计算结果与Hspice仿真结果的误差小于3%,具有很高的精度,适合应用于大规模互连网络中的功耗估算和热分析. With the integrated circuits processing stepping into nanometer scale,the interconnect Joule heat becomes significantly large.Based on the RLC π equivalent circuit,this paper proposes a novel accurate model to evaluate Joule heat power of interconnected line in VLSI.The shielding effect of the inductor and the non-ideal step stimulation are considered in the proposed model.The power consumption of a typical interconnected topology in 90 nm complementary metal-oxide semiconductor process is computed.The error between results of this proposed method and Hspice simulation is within 3% when the input signal's delay time is within 1 ns.The proposed model can be used to estimate Joule heat consumption where rough heat control is needed,such as route structure in the network on chip.
出处 《物理学报》 SCIE EI CAS CSCD 北大核心 2010年第7期4895-4900,共6页 Acta Physica Sinica
基金 国家自然科学基金(批准号:60725415 60971064) 国家高技术研究发展计划(批准号:2009AA01Z258 2009AA01Z260) 西安AM创新基金(批准号:XA-AM-200907)资助的课题~~
关键词 互连线 焦耳热 动态功耗 RLCπ型等效模型 interconnected line Joule heat dynamic power consumption RLC π equivalent circuit
  • 相关文献

参考文献3

二级参考文献26

  • 1董大为.光学光刻的过去、现在和未来[J].中国集成电路,2004,13(7):65-68. 被引量:5
  • 2International Semiconductor Industry Association 2007 InternationalTechnology Roadmap for Semiconductors 2007 ( ITRS 2007).
  • 3Clark N T,Sujit D 2001 ACM/IEEE 38^th Design Automation Conf. Las Vegas, NV, USA, June 18-22,2001 p754.
  • 4Uchino T, Cong J 2002 IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 21 763.
  • 5Shin Y S,Sakurai T 2002 IEEE Trans . on Computer-Aided Design of Integrated Circuits and Systems 21 739.
  • 6Zhou Q M,Elmore K M 2006 ACM/IEEE 43^th Design Automation Conf. San-Francisco, CA, USA, July 24--28,2006 p965.
  • 7Chen G Q, Friedman E G 2008 IEEE Trans. on Circuits and Systems- II 55 26.
  • 8Soteriou V, Eisley N 2007 ACM Trans. on Architecture and Code Optimization 4 1544.
  • 9Ajami A H, Banerjee K 2001 ACM/IEEE 38^th Design Automation Conf. I.as Vegas, NV, USA, June 18--22,2001 p567.
  • 10Ajami A H, Banerjee K 2005 IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 2,4 849.

共引文献10

同被引文献26

  • 1Europe,Japan,Korea,Taiwan,USA.Semiconductor Industry Association 2012 International Technology Roadmap for Semiconductors 2012[DB/OL].[2013-01-02].http://www.itrs.net.zdz.
  • 2Uchino T,Cong J.An Interconnect Energy Model Considering Coupling Effects[J].IEEE Transactions Computer-Aided Design of Integration Circuits System,2002,21(7):763-776.
  • 3Sahoo S,Datta M,Kar R.An Efficient Dynamic Power Estimation Method for On-Chip VLSI Interconnects[C]//Proceedings of the 2nd International Conference on Emerging Applications of Information Technology.Piscataway:IEEE,2011:379-382.
  • 4Zhou Q,Mohanram K.Elmore Model for Energy Estimation in RC Trees[C]//43rd ACM/IEEE Design Automation Conference.Piscataway:IEEE,2006:965-970.
  • 5Kar R,Maheshwari V,Mondal S,et al.A Novel Power Estimation Method for On-Chip VLSI Distributed RLCG Global Interconnects Using Model Order Reduction Technique[C]//International Conference on Advances in Computer Engineering.Piscataway:IEEE,2010:105-109.
  • 6Chen C P,Chen Y P,Wong D F.Optimal Wire-Sizing Formula Under the Elmare Delay Model[C]//Proceedings of 33rd Design Automation Conference.Piscataway:IEEE,1996:487-490.
  • 7Lee Y M,Chen C C P,Wong D F.Optimal Wire-Sizing Function Under the Elmore Delay Model with Bounded Wire Sizes[J].IEEE Transactions Circuits System-Ⅰ:Fundamental Theory and Application,2002,49(11):1671-1677.
  • 8EI Moursy M A,Friedman E G.Exponentially Tapered H-Tree Clock Distribution Networks[J].IEEE Transactions Very Large Scale Integration System,2005,13(8):971-975.
  • 9Ni M,Memik S O.Self-Heating Aware Optimal Wire Sizing Under Elmore Delay Model[C]//Proceedings of Design,Automation and Test in Europe Conference and Exhibition.Piscataway:IEEE,2007:1373-1378.
  • 10Kar R,Maheshwari V,Agarwal V,et al.Modeling of RLC Interconnect Delay for Ramp Input Using Diffusion Model Approach[C]//IEEE Symposium on Industrial Electronics and Applications.Piscataway:IEEE,2010:436-440.

引证文献3

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部