基于SIMD结构的多标准LDPC译码器的VLSI实现

VLSI Implementation of Multi-Standard LDPC Decoder Based on SIMD Architecture

近年来,支持多标准的LDPC译码器已逐渐成为研究的热点.与传统译码器相比,所设计的LDPC译码器具有以下优点:1.实现了一个码率、码长可配置结构,进而可以支持多种标准;2.采用了一种改进型TPMP算法,使译码器的存储器容量大大减少,避免了因分块LDPC码的非规则性所造成的数据冲突问题;3.采用基于SIMD处理器的硬件结构,实现了硬件的高度规整性,易于芯片布局布线;4.设计了一个6级可配置流水线,可分时构造校验节点处理单元和变量节点处理单元,提高了硬件利用率和系统数据吞吐率.用这种架构实现了一个同时支持CMMB和DTMB两个标准的多标准LDPC译码器;芯片规模为75万门,时钟频率为220MHz,数据吞吐率为300Mbps.

Recently the LDPC decoder that could support multi-standard has become a major topic in the research of wireless communication system. Compared with traditional LDPC decoders, the proposed design in this paper has several merits as follows： 1. the novel decoder achieves a reconfigurable architecture for multiple code rates and data lengths, which consequently could support multi-standard schemes; 2. using a modified TPMP algorithm, the decoder largely reduces the memory size and avoids the data collision as a result of unstructured block-LDPC codes; 3. an architecture based on SIMD processor structure has been adopted to implement a high regular architecture which is convenient for chip layout; 4. enhancing the hardware resources utilization and gaining a higher system throughput by designing a dynamically reconfigurable 6-stage pipelined processing unit that can be configured into CNUs or VNUs by time-division multiplexing. A multi-standard LDPC decoder which supports both CMMB and DTMB standards has been synthesized on SMIC 0.13μm 1.2V 8-metal layer CMOS technology, the area of the decoder is about 0.75 million equivalent gates and the maximum operating clock frequency is 220MHz resulting in a decoding throughput of 300 Mbps. The proposed architecture can be applied to other multi-standard LDPC decoder schemes, such as an integration of IEEE 802.16e （WiMAX） and IEEE 802. lln （WLAN）, etc.