分数延迟FIR滤波器设计及FPGA实现

Design and Implementation of Fractional Delay FIR Filte Based on FPGA

分数延迟FIR滤波器有能改变频率响应特性的优点,但是分数延迟FIR滤波器对系数变化十分敏感且其系数无对称关系,所以实现分数延迟FIR滤波器相对实现FIR滤波器消耗的硬件资源多得多。FPGA有丰富的内部逻辑资源,完全能满足分数延迟FIR滤波器设计的需要。本文提出基于分布式算法和CSD码量化设计分数延迟FIR滤波器。基于分布式算法设计分数延迟FIR滤波器是将乘法运算转换为查找表操作并结合流水线技术节省硬件资源,提升处理速度;CSD码量化滤波器系数使其表示码中0最多,这样设计实现滤波器的硬件规模会大大减少,运算速度也会提高。硬件仿真结果表明此两种方法可行且高效。

Fractional delay filter is able to change its frequency response. But it is sensitive to its coefficients and its coefficients are not symmetric. So much more hardware resources is used to implement the fractional delay FIR filter than the FIR filter. FPGA is rich in logic resource. Therefore it can reach the need of design the fractional delay FIR filter. Based on more excellent arithmetic,the distributed arithmetic and canonic signed digit encoding method are presented to design fractional delay filter. Multiplication operation is transformed to look-up table operation and combining with pipelining technology to reduce hardware resources using and improve processing speed,based on distributed arithmetic. Canonic signed digit encoding makes the zeros of the binary digital which express the coefficients of the filter most. That will reduce scale of hardware greatly and improve operation speed. We can see both of the two methods are viable and high efficiency from the results of simulation.