铁电存储单元的设计和测试

The Design and Testing of a Ferroelectric Memory Cell

基于被应用于实际设计之中的统一的铁电器件模型，详细讨论了２Ｔ２Ｃ组态的铁电破坏性读出存储器单元的设计。在此基础上，设计和制造了分立元件的单元测试电路。通过与普通电容的对比实验，证实了铁电破坏性读出随机读取存储器与普通随机读取存储器不同的工作原理和模式。进而获得了被测ＦＲＡＭ单元的特性波形和铁电材料存储特性的有关数据。这些工作为进一步进行大规模铁电存储器的研究作了准备。

Based on the unified ferroelectric device model which is applied practically to the design, the 2T 2C configuration of the ferroelectric DRO memory cell is discussed in detail. A testing circuit for FRAM cell by using discrete devices is designed and made. It is verified that the working principle and mode of the ferroelectric DRO memory cell are different from the common RAM cell through the comparison between ferroelectric and general capacitance. In addition to that, we observed the characteristic waves of the FRAM memory cell which is undergoing the test and gathered the data of the ferroelectric materials memorizing performance. These results will be the basis of our further research work on the integrated ferroelectric memory.