研究多芯片组件互连延迟的一种新方法

A New Approach to the Investigation of Interconnection Delay for Multichip Modules

延迟与冲激响应的矩有密切的关系，文中给出了建立在前三个矩基础上的多芯片组件互连延迟模型。该模型揭示了非单调输出树状结构ＭＣＭ互连网络的延迟与各设计参数之间的明确关系，因此它可以作为一种计算延迟的有效方法。进一步的研究结果还给出了输出响应与各设计参数之间的关系式，因此该模型又为研究面向性能的布局、布线算法中的有关问题提供了一种解决的途径。

Moments of the system transfer function are closely related with the interconnection delays. Based on the first three moments, this paper presents the delay model for MCM interconnection network. The model reveals an explicit causal relationship between delay of non monotonic rising node voltage in tree structured and design parameters. Our results not only provide a viable new method for computing interconnection delay, more importantly, but also present a critical link between signal responses and design parameters. Finally, these formulas provide a tool to solve problems in the study of performance driven layout and routing algorithms.