同步时序网络的快速设计法

A Speedy Design for Synchronous Sequential Networks

数字电子技术中,时序网络的设计比较复杂.这是因为时序网络中还包含有记忆单元用以记住作用于该网络各输入信号的过去情况,并以状态变量的形式反馈于时序网络的输入.本文提出一种通用的网络结构以及怎样满足各种不同逻辑功能要求时,如何去编制网络中PROM中的数据.

In digital electronic technique the design of sequential networks is relatively complicated because the sequential networks contain the memory unit that remembers the signals alreaady input into the networks and feeds them back to the input terminal of the networks in the form of situational variables. This paper puts forward a universal network configuaration as well as a method for presetting the data in the PROM to eatisfy the given logical requirements.