基于流水线映射的粗粒度可重构运算阵列电路设计

Circuit design of coarse-grained reconfigurable computing array based on pipelining mapping

媒体处理算法内在的并行性推动了媒体处理器朝着运算阵列架构的方向发展。在分析了算法映射对电路执行效果的影响后,将运算阵列设计与算法映射相结合,针对如何有效利用阵列提出了一种流水线映射的方案,并分析了该映射方法对系统性能的影响。在此基础之上,以H.264中的IDCT算法为例提取流水线模型,并基于该模型设计出了粗粒度的可重构阵列。实验结果表明,该阵列在功耗、速度、器件利用率等方面具有明显优势,具有较好的应用价值。

The inside parallelism of multi-media processing pushes development of processors to the architecture of computing array.After analyzing the effect of algorithm mapping on circuit execution,combining the computing array design with the algorithm mapping,this paper proposed a method called pipelining mapping in order to utilize array effectively,and the performance of system using this method was evaluated.Based on the pipeline model extracted from IDCT of H.264,a corse-grained reconfigurable array is built.The final experimental results showed the great advantage of this array in many aspects such as power,speed,use ratio of device and so on.