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一种面向高清视频的运动估计计算阵列的实现

Implementation of an efficient ME computing array for HDTV level video sequence
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摘要 运动估计计算阵列(ME)是视频编码器中不可或缺的重要部分,承担着编码器50%~80%的计算任务。实现了一种可以达到高清图像实时处理的可变块运动估计计算阵列。该阵列具有输入带宽需求低,计算效率高等优点,能够满足高清视频(1280×720@30 fps)的实时处理的需求。 ME computing array carries out up to 50%~80% computing loads of nowdays encoder and is a indispensable component of it.This paper proposes a VBSME computing array with high data reuse and high efficiency for realtime video encoder on HDTV level(1280×720@30fps).
作者 吴风鸣
出处 《信息技术》 2010年第6期161-163,共3页 Information Technology
关键词 运动估计计算阵列 可变块运动估计 高清视频 实时处理 ME computing array VBSME HDTV realtime processing
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参考文献5

  • 1Wang Y,Osteman J.Comparison of block-based and meshbased motion esti-mation algorithms[J].1995 in Proc.IEEE ISCAS,1995:1157-1160.
  • 2Yeo H,Hu Y.A novel modular systolic architexture for full-search block matching motion estimation[J].IEEE Transactions on Circuits and Systems for Video Technology,1995(5):407-416.
  • 3Surin K,Hu Y H.Frame-level pipe-lined motion estimation array processor[J].IEEE Transactions on Circuits and Systems for Video Technology,2001,11:248-251.
  • 4Liu L C.A Frame-level FSBM motion estimation architecture with large search range[C].IEEE Conference on Advanced Video and Signal Based Survei-llance.Miami:IEEE Computer Society,2003:327-333.
  • 5何卫锋,毛志刚.基于帧级流水脉动阵列结构的运动估计电路[J].电子学报,2005,33(8):1487-1491. 被引量:3

二级参考文献7

  • 1Yeo H, Hu Y H. A novel modular systolic array architecture for fullsearch block-matching motion eatimation[J]. IEEE Transactions on Circuits and Systems for Video Technology, 1995,5(5) :407 - 416.
  • 2Surin K, Hu Y H. Frame-levd pipelined motion estimation array processor[J]. IEEE Transactions on Circuits and Systems for Video Technology,2001,11(2) :248 - 251.
  • 3Liu L C,et al.A frame-level FSBM motion estimation architecture with large search range[A]. IEEE Canference on Advanced Video and Signal Based Surveillance[C]. Miami: IEEE Computer Society,2003.327- 333.
  • 4Lai Y K, Chen L G. A data-interlacing architecture with two-dimensional data-reuse for full-search block matching algorithm [ J ]. IEEE Transactions on Circuits and Systems for Video Technology, 1998, 8(2) : 124 - 127.
  • 5Chen Y K, Kung S Y. A systolic methodology with application to full-search block matching architectures [ J ]. The Journal of VLSI Signal Processing-System for Signal, Image, and Video Technology, 1998, 19(1):51-77.
  • 6Lee C Y,Lu M C.An efficient VLSI architecture for Full-search block matching algorithms[J]. Journal of VLSI Signal Processing, 1997, 15(3) :275 - 283.
  • 7Tuan J C,Chang T S,C W Jen. On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture [ J].IEEE Transactions on Circuits and Systems for Video Technology,2002,12(1):61-72.

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