基于SoC的智能可级联芯片设计

Design of smart cascaded chip based on technology of SoC

为解决存储测试系统的微体积和多种存储容量需求的问题,提出了一种基于片上系统(SoC)技术的智能可级联芯片通用结构。这种结构可外接多种传感器,允许芯片以级联方式扩充系统的存储容量,采用主—从控制方式,通过级联芯片间互相连接的2个引脚即可完成所有芯片内部存储器工作的自动控制和切换,不需外加控制芯片,外引线少,可靠性高。采用CMOS工艺进行设计实现工艺中的线宽是0.18μm,芯片内部包括12bitADC,控制模块,512k×12bit存储单元和接口。经实验该芯片体积微小,性能稳定,使用灵活,已成功应用于压力、加速度等参数的测试。

A novel generic architecture of smart cascaded chip based on technology of system on chip （SoC） is presented. This structure can be connected to different sensors and allows chip adopting cascade to expand the storage capacity of the system. Master-slave control merle is used, the operations of all cascade chips＇ memory are controlled and switched automatically by master chip through the intereonnection between two pins of cascade-chip. This mode of extended memory has fewer lines between different chips, higher reliability and lower power consumption compared with traditional method. The chip is designed and realized by CMOS technology with a line width 0.18μm and 12 bit analog to digital converter （ADC） is integrated, control module,512 k× 12 bit static random access memory（SRAM） and interface. Experimental results show the system composed of cascaded chips has the advantage of small in size, stable characteristics, flexibility. It has already applied in pressure and acceleration measurement.