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一种硅埋置型系统级封装中集成毫米波无源器件工艺

Process development of millimeter- wave integrated passive devices on Si -based embedded system in package
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摘要 本文研究了一种基于低阻硅埋置腔体和BCB/Au金属布线的系统级封装技术,改进了介质层BCB在有腔体硅衬底上的第一次旋涂工艺。利用25um厚的BCB介质层,在低阻硅衬底上设计、制作了微带传输线(MSL)、接地共面波导线(CPWG),测试发现具有理想的传输性能:标准50欧姆微带传输线,在20-30GHz频带内插入损耗小于0.08dB/mm,回波损耗大于32dB/mm。在此基础上基于薄膜微带线结构设计、制作了一种应用于K波段雷达前端系统集成功分器,面积约为1.6×0.84mm^2,插入损耗小于0.45dB,端口回波损耗大于25dB。 In this paper, we have developed a process to fabricate BCB/Au muhilayer stack on low loss silicon based on the embedded package structure, especially for the dielectrical layer's spin - coating at the first time on the silicon substrate. We have designed, fabricated and characterized transmission lines, including micro - strip and coplanar waveguide lines. They have excellent performance : insertion loss and return loss of the standard 50 - Ohm micro - strip line are better than 0. 08dB/mm and 32dB/mm during the 20 - 30GHz band. Also, we have fabricated a power divider using thin - film micro - strip line for the SIP of the front - end of a radar working at K - Band. This fabricated power divider is just 1.6 * 0. 84mm^2, with insertion loss less than 0.45dB and return loss better than 25dB.
出处 《功能材料与器件学报》 CAS CSCD 北大核心 2010年第3期294-298,共5页 Journal of Functional Materials and Devices
关键词 系统级封装(SIP) 微带传输线 共面波导线 功分器 System In Package (SIP) Micro - strip line CPWG Power divider
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