一种基于先行DLMS的自适应滤波器的FPGA实现

FPGA implementation of adaptive filter based on look-ahead DLMS

本文阐述了自适应滤波器的基本原理,给出了先行DLMS算法的计算公式,该算法相对于DLMS而言只在系数更新计算路径上引入一个延迟,自适应滤波器仍能保持收敛,并在MATLAB平台上验证该算法在阶数小的自适应滤波器设计中的可行性。针对现今对高速数字信号处理的要求,提出了一种自适应滤波器的FPGA实现方法,在先行DLMS的基础上,加入流水线结构,采用VerilogHDL硬件描述语言编写底层代码,设计了一个两阶的自适应滤波器。最后在QuartusⅡ中进行仿真和时序分析,该设计可以显著地提高运算速率。

The paper explain the basic principle of adaptive filter and present Look-ahead DLMS algorithm. The algorithm introduce a delay only in the coefficient update path compared with DLMS algorithm and the ADF is still stable. We test and verify the feasibility of the algorithm by using it in short-tap adaptive filter in MATLAB. Faced with the requirement of high-speed digital signal progressing, we bring up an implementation of ADF based on FPGA and design a two-tap adaptive filter using Look-ahead DLMS algorithm with pipelining, then we write the codes with Verilog HDL. In the end, we do the simulation and the timing analysis in QuartusⅡ. It is concluded that the design can significantly improve the speed of operation.