一种适用于H.264标准的高度并行双层流水线结构CAVLC编码器

Design of a Highly Parallel and Double-Level Pipelined CAVLC Encoder for H.264

本文提出一种适用于H.264编码器的高度并行、双层流水线的CAVLC硬件实现结构.该结构设计了四路并行扫描统计模块,克服了以往结构每个时钟周期只能扫描一个系数的处理速率瓶颈;通过使用FIFO,平衡每一级流水线的处理延时,提高整个流水线工作的效率;在各个编码模块内部也大量采用流水线结构,提高数据吞吐率.基于0.18μm CMOS工艺,新结构在166.7MHz工作频率下,综合等效门数为20685门,数据吞吐率为每秒处理27M系数块,甚至能够实时编码数字影视格式的视频(4096×2048@30fp/s).整个设计在数据吞吐率提高到以往结构的3.46倍的同时,硬件资源代价并没有显著的增加.

This paper presents the design of a CAVLC encoder for H.264 featuring a highly parallel and double-level pipelined architecture.In order to overcome the speed bottleneck of one coefficient per cycle during scanning,the proposed design uses four-channel parallel processing instead of serial scanning.And the delays of all stages in the pipelined architecture are averaged by FIFOs,which achieves a high efficiency for the entire pipeline.The pipelined structure is also widely used in sub-modules for higher throughput.Based on 0.18μm CMOS technology,the proposed architecture is synthesized into 20685 logic gates and achieved average 27M blocks/s at 166.7MHz frequency,and even meets the requirements of real-time processing of digital cinema video（4096×2048@30fp）.The date throughput of the proposed architecture is 3.46 times of that of the previous reported work with acceptable increase in area.