基于Virtex-Ⅱ的时钟数据恢复电路的设计

The Design of CDR Circuit Based on Virtex-Ⅱ

高性能的通信质量要求高稳定性和高精度的时钟,然而在传输过程中不可避免会出现时钟的抖动。这些抖动就给传输带来了偏差,因此,对于时钟的恢复是非常有必要的。基于Virtex系列FPGA,设计了用于时钟数据恢复的电路,经验证该设计电路能有效地恢复输入的时钟数据信号。

An efficient communication requires high stability and high-precision clock,but the clock jitter is inevitable during the transmission.There will be some deviations because of the jitters,so the recovery of the clock is quite necessary.Based on Virtex serial FPGA of Xilinx Company,a circuit is designed which is used to recovery the input clock and data.And it can recover the clock and data efficient by verification.