摘要
基于串行累加抵消结构,提出了一种简单的多符号相干累加方案。该方案可用于直扩通信系统接收机中,以提高相关峰的检测信噪比和伪码捕获概率。分析了多符号相干累加器增强直扩信号伪码捕获性能的基本原理,讨论了所提方案的设计思路和实现问题。计算机仿真和FPGA实现证明,与经典的并行分级相加累加器相比,所提方案在不降低伪码捕获性能的基础上,具有非常低的硬件复杂度,且输出时延较小。
Based on serial accumulation and elimination structure, a novel multi-symbol coherent accumulator is proposed. It can be applied to DSSS （Direct Sequence Spreading Spectrum） receivers to improve detection performance as well as the acquisition probability of PN （Pseudo Noise） codes. The corresponding mechanism and design problems of the scheme are discussed in detail. Theoretical analyses and FPGA implementations show that it has lower hardware complexity and less delay than the classical parallel cascade accumulation scheme.
出处
《无线电工程》
2010年第7期13-15,31,共4页
Radio Engineering
