高速数字印制电路板电源面/地面层结构对ΔI噪声抑制的研究

Restriction on Delta I Noise Along the Power/Ground Layer on the Highspeed Digital Printed Circuit Board

在高速数字印制电路板（ＰＣＢ）上，在间距很小的电源面地面之间存在着一个层电容（一般为０．０２～２００ｎＦ），该层电容对ΔＩ噪声有抑制作用．本文采用混合位积分方程法（ＭＰＩＥ）和矩量法（ＭｏＭ）建立了一个计算模型，从定量的角度分析和描述了在高频时（１００ＭＨｚ～３ＧＨｚ）ＰＣＢ板的电源面／地面层结构对ΔＩ噪声的作用．与实测数据相对比，该方法具有较高的精确度．并采用该方法定量地分析ＰＣＢ板的电源面／地面层结构参数对ΔＩ噪声的影响，据此提出了在高频时减小ΔＩ噪声的具体方法．

On the hihgspeed digital printed circuit board (PCB),there exists a layer capacitance (generally from 0.02nF to 200nF) between the closely spaced power and ground layers,which has some resrtiction on delta I noise.According to MPIE (Mixed Potential Integral Equation) and MoM(Method of Moment),a model is developed to analyze and characterize quantitatively the restriction on delta I noise by the power/ground structure on PCB in high frequencies (from 100MHz to 3GHz).In comparison with the measured data from a testboard,the method produces relatively precise results.And several strategies are provided to reduce the delta I noise in high frequencies.